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CC2500 calibration http://e2e.ti.com/support/low_power_rf/f/155/p/28598/99607.aspx#99607

PLL Lock check during Transmission for CC1020

http://e2e.ti.com/support/low_power_rf/f/155/p/61084/218982.aspx

CC2500 calibration http://e2e.ti.com/support/low_power_rf/f/155/p/28598/99607.aspx#99607

このフォーラム質問文の中で、Calibrationを実行後に、GDOピンの0x0A機能で、PLLのLOCKが完了したのかどうかを判断しているとの書き込みがある。

0x0Aの機能にはこのようなものだとのこと。（CC1101 detasheet P.60 Table41 GDOx Signal Selection）

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.

この、PLLがLOCKの状態かを判断できるというGDOピンの0x0Aの機能の説明は、cc1101のデータシートのPage56の”22 VCO”について記述がある。

22.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC1101 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 34 on page 52. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC1101 Errata Notes 4. For more robust operation, the source code could include a check so that the PLL is recalibrated until PLL lock is achieved if the PLL does not lock the first time.