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Project DescriptionThis utility is very useful for those designer(s) who does not know the order of their RTL files and/or does not know which file to compile in which library. It takes all the RTL files as input and then process those files internally and come up with a sorted/ordered list of files along with their proper VHDL /Vlog work library. It takes a input file which contains all the Verilog and/or VHDL files(one file per line without any * or regular expression ). You can simply redirect the output of the 'ls' command to create this file. Make sure that there is no special character e.g. '*' or '@' in the name of files. After processing all the listed files it will finally create a modelsim compilation script named 'modelsim_compile.csh'. This script can be used as reference to create compilation script for any other simulator. It supports complex constructs like VHDL configuration and works fine even if the inut VHDL / Verilog has syntax or semantic errors.