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rmassignments

Project Description

Reduces / Removes concurrent assignment statements from a verilog design without changing the design functionality.

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Latest Files
- removeassignments-25DEC2012.zip (Date: 2012-12-26, Size: 24.3 MB)
- removeassignments-25DEC2012.tar.gz (Date: 2012-12-26, Size: 24.3 MB)
- removeassignments-30OCT2012.zip (Date: 2012-12-02, Size: 24.0 MB)
- removeassignments-30OCT2012.tar.gz (Date: 2012-12-02, Size: 24.0 MB)
- removehierarchy-30SEP2012.tar.gz (Date: 2012-09-30, Size: 14.9 MB)

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Project Informations

Last Update
- 2012-01-19 19:13

Registered
- 2012-01-18

Project Ranking
- Activity Ranking: Out of ranking

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